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1 LTC1604 high speed, 16-bit, 333ksps sampling a/d converter with shutdown applicatio n s u the ltc ? 1604 is a 333ksps, 16-bit sampling a/d con- verter that draws only 220mw from 5v supplies. this high performance device includes a high dynamic range sample-and-hold, a precision reference and a high speed parallel output. two digitally selectable power shutdown modes provide power savings for low power systems. the LTC1604s full-scale input range is 2.5v. outstand- ing ac performance includes 90db s/(n+d) and C 100db thd at a sample rate of 333ksps. the unique differential input sample-and-hold can acquire single-ended or differential input signals up to its 15mhz bandwidth. the 68db common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. the adc has m p compatible,16-bit parallel output port. there is no pipeline delay in conversion results. a separate convert start input and a data ready signal (busy) ease connections to flfos, dsps and microprocessors. features n a complete, 333ksps 16-bit adc n 90db s/(n+d) and C100db thd (typ) n power dissipation: 220mw (typ) n no pipeline delay n no missing codes over temperature n nap (7mw) and sleep (10 m w) shutdown modes n operates with internal 15ppm/ c reference or external reference n true differential inputs reject common mode noise n 5mhz full power bandwidth n 2.5v bipolar input range n 36-pin ssop package descriptio n u , ltc and lt are registered trademarks of linear technology corporation. typical applicatio n u frequency (khz) 0 amplitude (db) 120 1604 ta02 40 80 160 0 20 40 60 80 100 120 140 20 60 100 140 f sample = 333khz f in = 100khz sinad = 89db thd = 96db LTC1604 4096 point fft n telecommunications n digital signal processing n multiplexed data acquisition systems n high speed data acquisition n spectrum analysis n imaging systems 2.2 f 10 f 10 f 10 47 f 4 6 differential analog input 2.5v refcomp 4.375v control logic and timing b15 to b0 16-bit sampling adc + 10 f 5v or 3v p control lines d15 to d0 output buffers 16-bit parallel bus 11 to 26 1604 ta01 ognd ov dd 28 29 1 2 a in + a in shdn cs convst rd busy 33 32 31 30 27 7.5k 3 36 35 10 9 5v 5v av dd av dd dv dd dgnd v ref 8 agnd agnd 7 agnd 5 agnd 34 ?v v ss 10 f 2.5v ref 10 f 1.75x + + + + + +
2 LTC1604 absolute m axi m u m ratings w ww u package/order i n for m atio n w u u order part number av dd = dv dd = ov dd = v dd (notes 1, 2) supply voltage (v dd ) ................................................ 6v negative supply voltage (v ss )................................ C 6v total supply voltage (v dd to v ss ) .......................... 12v analog input voltage (note 3) ......................... (v ss C 0.3v) to (v dd + 0.3v) v ref voltage (note 4) ................. C 0.3v to (v dd + 0.3v) refcomp voltage (note 4) ......... C 0.3v to (v dd + 0.3v) digital input voltage (note 4) ....................C 0.3v to 10v digital output voltage .................. C 0.3v to (v dd + 0.3v) power dissipation ............................................. 500mw operating temperature range LTC1604c............................................... 0 c to 70 c LTC1604i ............................................ C 40 c to 85 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c t jmax = 125 c, q ja = 95 c/w consult factory for military grade parts. cc hara terist ics co u verter with internal reference (notes 5, 6) LTC1604 LTC1604a parameter conditions min typ max min typ max units resolution (no missing codes) l 15 16 16 16 bits integral linearity error (note 7) l 1 4 0.5 2 lsb transition noise (note 8) 0.7 0.7 lsb offset error (note 9) l 0.05 0.125 0.05 0.125 % offset tempco (note 9) 0.5 0.5 ppm/ c full-scale error internal reference 0.125 0.25 0.125 0.25 % external reference 0.25 0.25 % full-scale tempco i out (reference) = 0, internal reference 15 15 ppm/ c LTC1604cg LTC1604ig LTC1604acg LTC1604aig symbol parameter conditions min typ max units v in analog input range (note 2) 4.75 v dd 5.25v, C 5.25 v ss C 4.75v, 2.5 v v ss (a in C , a in + ) av dd i in analog input leakage current cs = high l 1 m a c in analog input capacitance between conversions 43 pf during conversions 5 pf t acq sample-and-hold acquisition time 380 ns t ap sample-and-hold acquisition delay time C 1.5 ns t jitter sample-and-hold acquisition delay time jitter 5 ps rms cmrr analog input common mode rejection ratio C 2.5v < (a in C = a in + ) < 2.5v 68 db put u i a a u log 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 top view g package 36-lead plastic ssop 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 av dd av dd v ss shdn cs conv rd ov dd ognd busy d0 d1 d2 d3 d4 d5 d6 d7 a in + a in v ref refcomp agnd agnd agnd agnd dv dd dgnd d15 (msb) d14 d13 d12 d11 d10 d9 d8
3 LTC1604 dy a ic accuracy u w (note 5) LTC1604 LTC1604a symbol parameter conditions min typ max min typ max units s/n signal-to-noise ratio 5khz input signal l 90 87 90 db 100khz input signal 90 90 db s/(n + d) signal-to-(noise + distortion) ratio 5khz input signal 90 90 db 100khz input signal (note 10) l 89 84 89 db thd total harmonic distortion 5khz input signal C100 C 100 db up to 5th harmonic 100khz input signal l C94 C94 C88 db sfdr spurious free dynamic range 100khz input signal 96 96 db imd intermodulation distortion f in1 = 29.37khz, f in2 = 32.446khz C 88 C 88 db full power bandwidth 5 5 mhz full linear bandwidth (s/(n + d) 3 84db 350 350 khz (note 5) parameter conditions min typ max units v ref output voltage i out = 0 2.475 2.500 2.515 v v ref output tempco i out = 0 15 ppm/ c v ref line regulation 4.75 v dd 5.25v 0.01 lsb/v C 5.25v v ss C 4.75v 0.01 lsb/v v ref output resistance 0 ? i out ? 1ma 7.5 k w refcomp output voltage i out = 0 4.375 v i ter al refere ce characteristics u u u symbol parameter conditions min typ max units v ih high level input voltage v dd = 5.25v l 2.4 v v il low level input voltage v dd = 4.75v l 0.8 v i in digital input current v in = 0v to v dd l 10 m a c in digital input capacitance 5pf v oh high level output voltage v dd = 4.75v, i out = C 10 m a 4.5 v v dd = 4.75v, i out = C 400 m a l 4.0 v v ol low level output voltage v dd = 4.75v, i out = 160 m a 0.05 v v dd = 4.75v, i out = 1.6ma l 0.10 0.4 v i oz hi-z output leakage d15 to d0 v out = 0v to v dd , cs high l 10 m a c oz hi-z output capacitance d15 to d0 cs high (note 11) l 15 pf i source output source current v out = 0v C 1 0 ma i sink output sink current v out = v dd 10 ma (note 5) digital i puts a d digital outputs u u
4 LTC1604 symbol parameter conditions min typ max units v dd positive supply voltage (notes 12, 13) 4.75 5.25 v v ss negative supply voltage (note 12) C 4.75 C 5.25 v i dd positive supply current cs = rd = 0v l 18 30 ma nap mode cs = 0v, shdn = 0v 1.5 2.4 ma sleep mode cs = 5v, shdn = 0v 1 100 m a i ss negative supply current cs = rd = 0v l 26 40 ma nap mode cs = 0v, shdn = 0v 1 100 m a sleep mode cs = 5v, shdn = 0v 1 100 m a p d power dissipation cs = rd = 0v l 220 350 mw nap mode cs = 0v, shdn = 0v 7.5 12 mw sleep mode cs = 5v, shdn = 0v 0.01 1 mw power require e ts w u ti i g characteristics u w (note 5) symbol parameter conditions min typ max units f smpl(max) maximum sampling frequency l 333 khz t conv conversion time l 1.5 2.45 2.8 m s t acq acquisition time (note 11) l 480 ns t acq+conv throughput time (acquisition + conversion) l 3 m s t 1 cs to rd setup time (notes 11, 12) l 0ns t 2 cs to convst setup time (notes 11, 12) l 10 ns t 3 shdn to cs - setup time (notes 11, 12) l 10 ns t 4 shdn - to convst wake-up time cs = low (note 12) 400 ns t 5 convst low time (note 12) l 40 ns t 6 convst to busy delay c l = 25pf 36 ns l 80 ns t 7 data ready before busy - 60 ns l 32 ns t 8 delay between conversions (note 12) l 200 ns t 9 wait time rd after busy - (note 12) l C5 ns t 10 data access time after rd c l = 25pf 40 50 ns l 60 ns c l = 100pf 45 60 ns l 75 ns t 11 bus relinquish time 50 60 ns LTC1604c l 70 ns LTC1604i l 75 ns t 12 rd low time (note 12) l t 10 ns t 13 convst high time (note 12) l 40 ns t 14 aperture delay of sample-and-hold 2 ns (note 5)
5 LTC1604 the l denotes specifications that apply over the full operating temperature range. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to ground with dgnd, ognd and agnd wired together unless otherwise noted. note 3: when these pin voltages are taken below v ss or above v dd , they will be clamped by internal diodes. this product can handle input currents greater than 100ma below v ss or above v dd without latchup. note 4: when these pin voltages are taken below v ss , they will be clamped by internal diodes. this product can handle input currents greater than 100ma below v ss without latchup. these pins are not clamped to v dd . note 5: v dd = 5v, v ss = C 5v, f smpl = 333khz, and t r = t f = 5ns unless otherwise specified. note 6: linearity, offset and full-scale specification apply for a single- ended a in + input with a in C grounded. ti i g characteristics u w (note 5) note 7: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 8: typical rms noise at the code transitions. see figure 17 for histogram. note 9: bipolar offset is the offset voltage measured from C 0.5lsb when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111. note 10: signal-to-noise ratio (snr) is measured at 5khz and distortion is measured at 100khz. these results are used to calculate signal-to-nosie plus distortion (sinad). note 11: guaranteed by design, not subject to test. note 12: recommended operating conditions. note 13: the falling convst edge starts a conversion. if convst returns high at a critical point during the conversion it can create small errors. for best performance ensure that convst returns high either within 250ns after conversion start or after busy rises. typical perfor m a n ce characteristics uw spurious-free dynamic range vs input frequency input frequency (hz) 0 10 20 30 40 50 60 70 80 90 100 110 spurious-free dynamic range (db) 1604 g05 1k 10k 100k 1m input frequency (hz) 0 10 20 30 40 50 60 70 80 90 100 110 amplitude (db below the fundamental) 1604 g04 1k 10k 100k 1m thd 3rd 2nd distortion vs input frequency frequency (hz) 100 90 80 70 60 50 40 30 20 10 0 signal-to-noise ratio (db) 1604 g03 1k 10k 100k 1m signal-to-noise ratio vs input frequency code inl (lsb) ?2768 ?6384 0 16384 32767 1604 g11 2.0 1.5 1.0 0.5 0.0 ?.5 ?.0 ?.5 ?.0 integral nonlinearity vs output code code ?2768 ?6384 16384 32767 dnl (lsb) 1604 g10 1.0 0.8 0.6 0.4 0.2 0.0 ?.2 ?.4 ?.6 ?.8 ?.0 0 differential nonlinearity vs output code frequency (hz) 1k sinad (db) 100 90 80 70 60 50 40 30 20 10 0 10k 100k 1m 1604 g01 v in = 0db v in = 20db v in = 40db s/(n + d) vs input frequency and amplitude
6 LTC1604 typical perfor m a n ce characteristics uw input frequency (hz) 1k common mode rejection (db) 80 70 60 50 40 30 20 10 0 10k 100k 1604g09 1m input common mode rejection vs input frequency input frequency (hz) 1k amplitude of power supply feedthrough (db) 0 20 40 60 80 100 120 10k 100k 1m 1604 g07 f sample = 333khz v ripple = 10mv v ss a vdd power supply feedthrough vs ripple frequency pi n fu n ctio n s uuu a in + (pin 1): positive analog input. the adc converts the difference voltage between a in + and a in C with a differen- tial range of 2.5v. a in + has a 2.5v input range when a in C is grounded. a in C (pin 2): negative analog input. can be grounded, tied to a dc voltage or driven differentially with a in + . v ref (pin 3): 2.5v reference output. bypass to agnd with 2.2 m f tantalum in parallel with 0.1 m f ceramic. refcomp (pin 4): 4.375 reference compensation pin. bypass to agnd with 47 m f tantalum in parallel with 0.1 m f ceramic. agnd (pins 5 to 8): analog grounds. tie to analog ground plane. dv dd (pin 9): 5v digital power supply. bypass to dgnd with 10 m f tantalum in parallel with 0.1 m f ceramic. dgnd (pin 10): digital ground for internal logic. tie to analog ground plane. d15 to d0 (pins 11 to 26): three-state data outputs. d15 is the most significant bit. busy (pin 27): the busy output shows the converter status. it is low when a conversion is in progress. data is valid on the rising edge of busy. ognd (pin 28): digital ground for output drivers. ov dd (pin 29): digital power supply for output drivers. bypass to ognd with 10 m f tantalum in parallel with 0.1 m f ceramic. rd (pin 30): read input. a logic low enables the output drivers when cs is low. convst (pin 31): conversion start signal. this active low signal starts a conversion on its falling edge when cs is low. cs (pin 32): the chip select input. must be low for the adc to recognize convst and rd inputs. shdn (pin 33): power shutdown. drive this pin low with cs low for nap mode. drive this pin low with cs high for sleep mode. v ss (pin 34): C 5v negative supply. bypass to agnd with 10 m f tantalum in parallel with 0.1 m f ceramic. av dd (pin 35): 5v analog power supply. bypass to agnd with 10 m f tantalum in parallel with 0.1 m f ceramic. av dd (pin 36): 5v analog power supply. bypass to agnd with 10 m f tantalum in parallel with 0.1 m f ceramic and connect this pin to pin 35 with a 10 w resistor. intermodulaton distortion frequency (khz) 020 amplitude (db) 80 100 0 20 40 60 80 100 120 140 1604 g06 40 60 160 120 140 f sample = 333khz f in1 = 29.3khz f in2 = 32.4khz
7 LTC1604 uu w fu ctio al block diagra test circuits load circuits for access timing load circuits for output float delay 1k (a) hi-z to v oh and v ol to v oh c l 1k 5v dn dn (b) hi-z to v ol and v oh to v ol c l 1604 tc01 1k (a) v oh to hi-z c l 1k 5v dn dn (b) v ol to hi-z c l 1604 tc02 2.2 f 10 f 10 f 10 47 f 4 6 differential analog input 2.5v refcomp 4.375v control logic and timing b15 to b0 16-bit sampling adc + 10 f 5v or 3v p control lines d15 to d0 output buffers 16-bit parallel bus 11 to 26 1604 ta01 ognd ov dd 28 29 1 2 a in + a in shdn cs convst rd busy 33 32 31 30 27 7.5k 3 36 35 10 9 5v 5v av dd av dd dv dd dgnd v ref 8 agnd agnd 7 agnd 5 agnd 34 ?v v ss 10 f 2.5v ref 10 f 1.75x + + + + + +
8 LTC1604 applicatio n s i n for m atio n wu u u conversion details the LTC1604 uses a successive approximation algorithm and internal sample-and-hold circuit to convert an analog signal to a 16-bit parallel output. the adc is complete with a sample-and-hold, a precision reference and an internal clock. the control logic provides easy interface to micro- processors and dsps. (please refer to the digital interface section for the data format.) conversion start is controlled by the cs and convst inputs. at the start of the conversion the successive approximation register (sar) resets. once a conversion cycle has begun it cannot be restarted. during the conversion, the internal differential 16-bit capacitive dac output is sequenced by the sar from the most significant bit (msb) to the least significant bit (lsb). referring to figure 1, the a in + and a in C inputs are acquired during the acquire phase and the comparator offset is nulled by the zeroing switches. in this acquire phase, a duration of 480ns will provide enough time for the sample-and-hold capacitors to acquire the analog signal. during the convert phase the comparator zeroing switches open, putting the comparator into compare mode. the input switches connect the c smpl capacitors to ground, transferring the differential analog input charge onto the + comp a in + c smpl hold sample a in c smpl +c dac +v dac ? dac ? dac hold hold sample hold sar output latches 16 d15 d0 1604 f01 ? ? zeroing switches figure 1. simplified block diagram summing junctions. this input charge is successively compared with the binary-weighted charges supplied by the differential capacitive dac. bit decisions are made by the high speed comparator. at the end of a conversion, the differential dac output balances the a in + and a in C input charges. the sar contents (a 16-bit data word) which represent the difference of a in + and a in C are loaded into the 16-bit output latches. digital interface the a/d converter is designed to interface with micropro- cessors as a memory mapped device. the cs and rd control inputs are common to all peripheral memory interfacing. a separate convst is used to initiate a con- version. internal clock the a/d converter has an internal clock that runs the a/d conversion. the internal clock is factory trimmed to achieve a typical conversion time of 2.45 m s and a maximum conversion time of 2.8 m s over the full temperature range. no external adjustments are required. the guaranteed maximum acquisition time is 480ns. in addition, a through- put time (acquisition + conversion) of 3 m s and a minimum sampling rate of 333ksps are guaranteed. 3v input/output compatible the LTC1604 operates on 5v supplies, which makes the device easy to interface to 5v digital systems. this device can also talk to 3v digital systems: the digital input pins (shdn, cs, convst and rd) of the LTC1604 recognize 3v or 5v inputs. the LTC1604 has a dedicated output supply pin (ov dd ) that controls the output swings of the digital output pins (d0 to d15, busy) and allows the part to talk to either 3v or 5v digital systems. the output is twos complement binary. power shutdown the LTC1604 provides two power shutdown modes, nap and sleep, to save power during inactive periods. the nap mode reduces the power by 95% and leaves only the digital logic and reference powered up. the wake-up time from nap to active is 200ns. in sleep mode all bias
9 LTC1604 applicatio n s i n for m atio n wu u u currents are shut down and only leakage current remains (about 1 m a). wake-up time from sleep mode is much slower since the reference circuit must power up and settle. sleep mode wake-up time is dependent on the value of the capacitor connected to the refcomp (pin 4). the wake-up time is 160ms with the recommended 47 m f capacitor. shutdown is controlled by pin 33 (shdn). the adc is in shutdown when shdn is low. the shutdown mode is selected with pin 32 (cs). when shdn is low, cs low selects nap and cs high selects sleep. figure 2a. nap mode to sleep mode timing t 3 shdn cs 1604 f02a t 4 shdn convst 1604 f02b figure 2b. shdn to convst wake-up timing t 2 t 1 cs convst rd 1604 f03 figure 3. cs top convst setup timing 0 change in dnl (lsb) 2800 1604 f04 400 800 1600 1200 2000 2400 4 3 2 1 0 convst low time, t 5 (ns) t conv t acq figure 4. change in dnl vs convst low time. be sure the convst pulse returns high early in the conversion or after the end of conversion timing and control conversion start and data read operations are controlled by three digital inputs: convst, cs and rd. a falling edge applied to the convst pin will start a conversion after the adc has been selected (i.e., cs is low). once initiated, it cannot be restarted until the conversion is complete. converter status is indicated by the busy output. busy is low during a conversion. we recommend using a narrow logic low or narrow logic high convst pulse to start a conversion as shown in figures 5 and 6. a narrow low or high convst pulse prevents the rising edge of the convst pulse from upset- ting the critical bit decisions during the conversion time. figure 4 shows the change of the differential nonlinearity error versus the low time of the convst pulse. as shown, if convst returns high early in the conversion (e.g., convst low time <500ns), accuracy is unaffected. simi- larly, if convst returns high after the conversion is over (e.g., convst low time >t conv ), accuracy is unaffected. for best results, keep t 5 less than 500ns or greater than t conv . figures 5 through 9 show several different modes of operation. in modes 1a and 1b (figures 5 and 6), cs and rd are both tied low. the falling edge of convst starts the conversion. the data outputs are always enabled and data can be latched with the busy rising edge. mode 1a shows operation with a narrow logic low convst pulse. mode 1b shows a narrow logic high convst pulse. in mode 2 (figure 7) cs is tied low. the falling edge of convst signal starts the conversion. data outputs are in
10 LTC1604 applicatio n s i n for m atio n wu u u (convst = ) figure 5. mode 1a. convst starts a conversion. data outputs always enabled data n d15 to d0 data (n + 1) d15 to d0 data (n ?1) d15 to d0 convst cs = rd = 0 busy 1604 f05 t 5 t conv t 6 t 8 t 7 data figure 7. mode 2. convst starts a conversion. data is read by rd convst cs = 0 busy 1604 f07 t 5 t conv t 8 t 13 t 6 t 9 t 12 data n d15 to d0 t 11 t 10 rd data data (n ?1) d15 to d0 convst busy 1604 f06 t conv t 6 t 13 t 7 cs = rd = 0 data n d15 to d0 data (n + 1) d15 to d0 data t 5 t 6 t 8 figure 6. mode 1b. convst starts a conversion. data outputs always enabled (convst = )
11 LTC1604 applicatio n s i n for m atio n wu u u rd = convst cs = 0 busy 1604 f08 t conv t 6 data (n ?1) d5 to d0 data data n d15 to d0 data (n + 1) d15 to d0 data n d15 to d0 t 11 t 8 t 10 t 7 rd = convst busy cs = 0 1604 f09 t conv t 6 data (n ?1) d15 to d0 data data n d15 to d0 t 10 t 11 t 8 figure 8. mode 2. slow memory mode timing figure 9. rom mode timing three-state until read by the mpu with the rd signal. mode 2 can be used for operation with a shared data bus. in slow memory and rom modes (figures 8 and 9) cs is tied low and convst and rd are tied together. the mpu starts the conversion and reads the output with the com- bined convst-rd signal. conversions are started by the mpu or dsp (no external sample clock is needed). in slow memory mode the processor applies a logic low to rd (= convst), starting the conversion. busy goes low, forcing the processor into a wait state. the previous conversion result appears on the data outputs. when the conversion is complete, the new conversion results appear on the data outputs; busy goes high, releasing the processor and the processor takes rd (= convst) back high and reads the new conversion data. in rom mode, the processor takes rd (= convst) low, starting a conversion and reading the previous conversion result. after the conversion is complete, the processor can read the new result and initiate another conversion. differential analog inputs driving the analog inputs the differential analog inputs of the LTC1604 are easy to drive. the inputs may be driven differentially or as a single- ended input (i.e., the a in C input is grounded). the a in + and a in C inputs are sampled at the same instant. any un- wanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sample- and-hold circuit. the inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. during conversion the analog inputs draw only a small leakage current. if the source impedance of the driving circuit is low, then the LTC1604 inputs can be driven directly. as source impedance in- creases so will acquisition time (see figure 10). for minimum acquisition time with high source impedance, a buffer amplifier should be used. the only requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion
12 LTC1604 applicatio n s i n for m atio n wu u u starts (settling time must be 200ns for full throughput rate). choosing an input amplifier choosing an input amplifier is easy if a few requirements are taken into consideration. first, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (< 100 w ) at the closed-loop band- width frequency. for example, if an amplifier is used in a gain of +1 and has a unity-gain bandwidth of 50mhz, then the output impedance at 50mhz should be less than 100 w . the second requirement is that the closed-loop bandwidth must be greater than 15mhz to ensure adequate small-signal settling for full throughput rate. if slower op amps are used, more settling time can be provided by increasing the time between conversions. the best choice for an op amp to drive the LTC1604 will depend on the application. generally applications fall into two categories: ac applications where dynamic specifi- cations are most critical and time domain applications where dc accuracy and settling time are most critical. the following list is a summary of the op amps that are suitable for driving the LTC1604. more detailed informa- tion is available in the linear technology databooks, the linearview tm cd-rom and on our web site at: www.linear-tech. com. figure 10. t acq vs source resistance lt ? 1007: low noise precision amplifier. 2.7ma supply current, 5v to 15v supplies, gain bandwidth product 8mhz, dc applications. lt1097: low cost, low power precision amplifier. 300 m a supply current, 5v to 15v supplies, gain bandwidth product 0.7mhz, dc applications. lt1227: 140mhz video current feedback amplifier. 10ma supply current, 5v to 15v supplies, low noise and low distortion. lt1360: 37mhz voltage feedback amplifier. 3.8ma sup- ply current, 5v to 15v supplies, good ac/dc specs. lt1363: 50mhz voltage feedback amplifier. 6.3ma sup- ply current, good ac/dc specs. lt1364/lt1365: dual and quad 50mhz voltage feedback amplifiers. 6.3ma supply current per amplifier, good ac/ dc specs. input filtering the noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC1604 noise and distortion. the small-signal band- width of the sample-and-hold circuit is 15mhz. any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. noisy input circuitry should be filtered prior to the analog inputs to minimize noise. a simple 1-pole rc filter is sufficient for many applications. for example, figure 11 shows a 3000pf capacitor from a in + to ground and a 100 w source resistor to limit the input bandwidth to 530khz. the 3000pf capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the adc input from sam- pling glitch sensitive circuitry. high quality capacitors and resistors should be used since these components can add distortion. npo and silver mica type dielectric capacitors have excellent linearity. carbon surface mount resistors can also generate distortion from self heating and from damage that may occur during soldering. metal film surface mount resistors are much less susceptible to both problems. linearview is a trademark of linear technology corporation. source resistance ( ) 1 10 100 1k 10k acquisition time ( m s) 10 1 0.1 0.01 1604 f10
13 LTC1604 applicatio n s i n for m atio n wu u u LTC1604 a in + a in v ref refcomp agnd 1604 f11 1 2 3 4 5 47 f 3000pf 100 analog input figure 11. rc input filter input range the 2.5v input range of the LTC1604 is optimized for low noise and low distortion. most op amps also perform well over this same range, allowing direct coupling to the analog inputs and eliminating the need for special transla- tion circuitry. some applications may require other input ranges. the LTC1604 differential inputs and reference circuitry can accommodate other input ranges often with little or no additional circuitry. the following sections describe the reference and input circuitry and how they affect the input range. internal reference the LTC1604 has an on-chip, temperature compensated, curvature corrected, bandgap reference that is factory trimmed to 2.500v. it is connected internally to a reference amplifier and is available at v ref (pin 3) (see figure 12a). a 7.5k resistor is in series with the output so that it can be easily overdriven by an external reference or other circuitry (see figure 12b). the reference amplifier gains the voltage at the v ref pin by 1.75 to create the required internal reference voltage. this provides buffering between the v ref pin and the high speed capacitive dac. the reference amplifier compensation pin (refcomp, pin 4) must be bypassed with a capacitor to ground. the reference amplifier is stable with capacitors of 22 m f or greater. for the best noise performance a 47 m f ceramic or 47 m f tantalum in parallel with a 0.1 m f ceramic is recom- mended. r2 12k r3 16k reference amp 47 f refcomp agnd v ref r1 7.5k 3 4 5 2.500v 4.375v LTC1604 1604 f12a bandgap reference figure 12a. LTC1604 reference circuit 1 2 3 0.1 m f 10 m f analog input 1604 f12b lt1019a-2.5 v out v in 5v a in + a in v ref LTC1604 agnd refcomp 5 4 + figure 12b. using the lt1019-2.5 as an external reference the v ref pin can be driven with a dac or other means shown in figure 13. this is useful in applications where the peak input signal amplitude may vary. the input span of the adc can then be adjusted to match the peak input signal, maximizing the signal-to-noise ratio. the filtering of the internal LTC1604 reference amplifier will limit the bandwidth and settling time of this circuit. a settling time of 20ms should be allowed for after a reference adjustment. differential inputs the LTC1604 has a unique differential sample-and-hold circuit that allows rail-to-rail inputs. the adc will always convert the difference of a in + C a in C independent of the common mode voltage (see figure 15a). the common mode rejection holds up to extremely high frequencies (see figure 14a). the only requirement is that both inputs
14 LTC1604 applicatio n s i n for m atio n wu u u LTC1604 a in + analog input 2v to 2.7v differential a in v ref refcomp agnd 1604 f13 1 2 3 4 5 47 m f ltc1450 2v to 2.7v figure 14a. cmrr vs input frequency input frequency (hz) 1k common mode rejection (db) 80 70 60 50 40 30 20 10 0 10k 100k 1604 g14a 1m figure 13. driving v ref with a dac can not exceed the av dd or v ss power supply voltages. integral nonlinearity errors (inl) and differential nonlin- earity errors (dnl) are independent of the common mode voltage, however, the bipolar zero error (bze) will vary. the change in bze is typically less than 0.1% of the common mode voltage. dynamic performance is also affected by the common mode voltage. thd will degrade as the inputs approach either power supply rail, from 96db with a common mode of 0v to 86db with a common mode of 2.5v or C 2.5v. differential inputs allow greater flexibility for accepting different input ranges. figure 14b shows a circuit that converts a 0v to 5v analog input signal with only an additional buffer that is not in the signal path. LTC1604 a in + a in v ref 0v to 5v 2.5v refcomp agnd 1604 f14b 1 2 3 4 5 10 f analog input + figure 14b. selectable 0v to 5v or 2.5v input range full-scale and offset adjustment figure 15a shows the ideal input/output characteristics for the LTC1604. the code transitions occur midway between successive integer lsb values (i.e., C fs + 0.5lsb, C fs + 1.5lsb, C fs + 2.5lsb,... fs C 1.5lsb, fs C 0.5lsb). the output is twos complement binary with 1lsb = fs C (C fs)/65536 = 5v/65536 = 76.3 m v. in applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. offset error must be adjusted before full-scale error. figure 15b shows the extra components required for full-scale error adjustment. zero offset is achieved by adjusting the offset applied to the a in C input. for zero offset error apply 1604 f15a 011...111 011...110 000...001 000...000 111...111 111...110 100...001 100...000 fs ?1lsb (fs ?1lsb) input voltage (a in + ? a in ) output code figure 15a. LTC1604 transfer characteristics
15 LTC1604 analog ground plane. no other digital grounds should be connected to this analog ground plane. low impedance analog and digital power supply common returns are essential to low noise operation of the adc and the foil width for these tracks should be as wide as possible. in applications where the adc data outputs and control signals are connected to a continuously active micropro- cessor bus, it is possible to get errors in the conversion results. these errors are due to feedthrough from the microprocessor to the successive approximation com- parator. the problem can be eliminated by forcing the microprocessor into a wait state during conversion or by using three-state buffers to isolate the adc data bus. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. the LTC1604 has differential inputs to minimize noise coupling. common mode noise on the a in + and a in C leads will be rejected by the input cmrr. the a in C input can be used as a ground sense for the a in + input; the LTC1604 will hold and convert the difference voltage between a in + and a in C . the leads to a in + (pin 1) and a in C (pin 2) should be kept as short as possible. in applications where this is not possible, the a in + and a in C traces should be run side by side to equalize coupling. supply bypassing high quality, low series resistance ceramic, 10 m f or 47 m f bypass capacitors should be used at the v dd and refcomp pins as shown in figure 16 and in the typical application on the first page of this data sheet. surface mount ceramic capacitors such as murata grm235y5v106z016 provide excellent bypassing in a small board space. alternatively, 10 m f tantalum capacitors in parallel with 0.1 m f ceramic capacitors can be used. bypass capacitors must be lo- cated as close to the pins as possible. the traces connect- ing the pins and the bypass capacitors must be kept short and should be made as wide as possible. applicatio n s i n for m atio n wu u u analog input 1604 f15b 1 2 3 r4 100 r7 50k r3 24k ?v r6 24k r8 50k r5 47k 4 5 0.1 f 47 f + a in + a in v ref refcomp agnd LTC1604 figure 15b. offset and full-scale adjust circuit C38 m v (i.e., C 0.5lsb) at a in + and adjust the offset at the a in C input until the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111. for full-scale adjustment, an input voltage of 2.499886v (fs/2 C 1.5lsbs) is applied to a in + and r2 is adjusted until the output code flickers between 0111 1111 1111 1110 and 0111 1111 1111 1111. board layout and grounding wire wrap boards are not recommended for high resolu- tion or high speed a/d converters. to obtain the best performance from the LTC1604, a printed circuit board with ground plane is required. layout should ensure that digital and analog signal lines are separated as much as possible. particular care should be taken not to run any digital track alongside an analog signal track or under- neath the adc.the analog input should be screened by agnd. an analog ground plane separate from the logic system ground should be established under and around the adc. pin 5 to pin 8 (agnds), pin 10 (adcs dgnd) and all other analog grounds should be connected to this single analog ground point. the refcomp bypass capacitor and the dv dd bypass capacitor should also be connected to this
16 LTC1604 applicatio n s i n for m atio n wu u u 1604 f16 a in + v ss ov dd dgnd av dd LTC1604 digital system analog input circuitry agnd 5 to 8 2 34 29 dv dd ognd 28 10 1 refcomp 4 47 m f v ref 3 2.2 m f a in 10 m f 36 10 m f av dd 35 10 m f 10 m f + 9 10 m f dc performance the noise of an adc can be evaluated in two ways: signal- to-noise raio (snr) in frequency domain and histogram in time domain. the LTC1604 excels in both. figure 18a demonstrates that the LTC1604 has an snr of over 90db in frequency domain. the noise in the time domain histo- gram is the transition noise associated with a high resolu- tion adc which can be measured with a fixed dc signal applied to the input of the adc. the resulting output codes are collected over a large number of conversions. the shape of the distribution of codes will give an indication of the magnitude of the transition noise. in figure 17 the distribution of output codes is shown for a dc input that has been digitized 4096 times. the distribution is gaussian and the rms code transition noise is about 0.66lsb. this corresponds to a noise level of 90.9db relative to full scale. adding to that the theoretical 98db of quantization error for 16-bit adc, the resultant corresponds to an snr level of 90.1db which correlates very well to the frequency domain measurements in dynamic performance section. dynamic performance the LTC1604 has excellent high speed sampling capabil- ity. fast fourier transform (fft) test techniques are used to test the adcs frequency response, distortions and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algorithm, the adcs spectral content can be examined for frequencies outside the fundamental. figures 18a and 18b show typical LTC1604 fft plots. code ? ? ? ? ? 0 1 2 3 4 5 count 2500 2000 1500 1000 500 0 1604 f17 figure 17. histogram for 4096 conversions frequency (khz) 0 amplitude (db) ?0 ?0 ?0 60 1604 f18a ?0 ?00 20 40 80 100 120 140 160 ?20 ?40 0 f sample = 333khz f in = 4.959khz sinad = 90.2db thd = ?03.2db figure 18a. this fft of the LTC1604s conversion of a full-scale 5khz sine wave shows outstanding response with a very low noise floor when sampling at 333ksps figure 16. power supply grounding practice
17 LTC1604 applicatio n s i n for m atio n wu u u signal-to-noise ratio the signal-to-noise plus distortion ratio [s/(n + d)] is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other frequency components at the a/d output. the output is band limited to frequencies from above dc and below half the sampling frequency. figure 18a shows a typical spectral content with a 333khz sampling rate and a 5khz input. the dynamic performance is excellent for input frequencies up to and beyond the nyquist limit of 167khz. effective number of bits the effective number of bits (enobs) is a measurement of the resolution of an adc and is directly related to the s/(n + d) by the equation: n = [s/(n + d) C 1.76]/6.02 where n is the effective number of bits of resolution and s/(n + d) is expressed in db. at the maximum sampling rate of 333khz the LTC1604 maintains above 14 bits up to the nyquist input frequency of 167khz (refer to figure 19). total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd log vvv vn v = +++ 20 234 1 222 2 ... where v1 is the rms amplitude of the fundamental fre- quency and v2 through vn are the amplitudes of the second through nth harmonics. thd vs input frequency is shown in figure 20. the LTC1604 has good distortion performance up to the nyquist frequency and beyond. frequency (khz) amplitude (db) ?0 ?0 ?0 1604 f18b ?0 ?00 ?20 ?40 0 060 20 40 80 100 120 140 160 f sample = 333khz f in = 97.152khz sinad = 89db thd = 96db frequency (hz) 1k effective bits sinad (db) 16 15 14 13 12 11 10 9 8 98 92 86 80 74 68 62 56 50 10k 100k 1m 1604 f19 figure 18b. even with inputs at 100khz, the LTC1604s dynamic linearity remains robust input frequency (hz) 0 10 20 30 40 50 60 70 80 90 100 110 amplitude (db below the fundamental) 1604 g04 1k 10k 100k 1m thd 3rd 2nd figure 20. distortion vs input frequency figure 19. effective bits and signal/(noise + distortion) vs input frequency
18 LTC1604 intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are applied to the adc input, nonlinearities in the adc transfer func- tion can create distortion products at the sum and differ- ence frequencies of mfa nfb, where m and n = 0, 1, 2, 3, applicatio n s i n for m atio n wu u u etc. for example, the 2nd order imd terms include (fa C fb). if the two input sine waves are equal in magni- tude, the value (in decibels) of the 2nd order imd products can be expressed by the following formula: imd fa fb log amplitude () = 20 at (fa fb) amplitude at fa peak harmonic or spurious noise the peak harmonic or spurious noise is the largest spec- tral component excluding the input signal and dc. this value is expressed in decibels relative to the rms value of a full-scale input signal. full-power and full-linear bandwidth the full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full-scale input signal. the full-linear bandwidth is the input frequency at which the s/(n + d) has dropped to 84db (13.66 effective bits). the LTC1604 has been designed to optimize input band- width, allowing the adc to undersample input signals with frequencies above the converters nyquist frequency. the noise floor stays very low at high frequencies; s/(n + d) becomes dominated by distortion at frequencies far beyond nyquist. frequency (khz) 020 amplitude (db) 80 100 0 20 40 60 80 100 120 140 1604 g06 40 60 160 120 140 f sample = 333khz f in1 = 29.3khz f in2 = 32.4khz figure 21. intermodulation distortion plot
19 LTC1604 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. dimensions in inches (millimeters) unless otherwise noted. package descriptio n u g package 36-lead plastic ssop (0.209) (ltc dwg # 05-08-1640) g36 ssop 1196 0.005 ?0.009 (0.13 ?0.22) 0 ?8 0.022 ?0.037 (0.55 ?0.95) 0.205 ?0.212** (5.20 ?5.38) 0.301 ?0.311 (7.65 ?7.90) 1234 5 6 7 8 9 10 11 12 14 15 16 17 18 13 0.499 ?0.509* (12.67 ?12.93) 25 26 22 21 20 19 23 24 27 28 29 30 31 32 33 34 35 36 0.068 ?0.078 (1.73 ?1.99) 0.002 ?0.008 (0.05 ?0.21) 0.0256 (0.65) bsc 0.010 ?0.015 (0.25 ?0.38) dimensions do not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimensions do not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * **
20 LTC1604 1604fa lt/tp 1098 rev a 2k ? printed in usa ? linear technology corporation 1998 typical applicatio n u linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com using the LTC1604 and two ltc1391s as an 8-channel differential 16-bit adc system d15 to d0 v ss agnd agnd agnd agnd refcomp 4.375v 11 to 26 1604 ta03 ch7 + + + + ch0 + 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 ltc1391 ltc1391 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 v + d v d out d in cs clk gnd ch7 ch0 1 f 5v d in cs clk ?v ?v 10 2.2 f 10 f 5v 10 f5v 10 34 9 35 36 3 4 10 f ?v 1 f 10 f 3000pf 3000pf 5 1 47 f a in + v ref av dd av dd dv dd dgnd ov dd ognd 28 p control lines 5v or 3v 10 f shdn cs convst rd busy 33 32 31 30 27 a in 2 67 8 1 f 5v 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 v + d v d out d in cs clk gnd 16-bit sampling adc + + + + + 1.75x 2.5v ref control logic and timing output buffers 16-bit parallel bus 7.5k LTC1604 b15 to b0 + 29 p control lines + related parts part number description comments ltc1410 12-bit, 1.25msps, 5v adc 71.5db sinad at nyquist, 150mw dissipation ltc1415 12-bit, 1.25msps, single 5v adc 55mw power dissipation, 72db sinad ltc1418 14-bit, 200ksps, single 5v adc 15mw, serial/para llel 10v ltc1419 low power 14-bit, 800ksps adc true 14-bit linearity, 81.5db sinad, 150mw dissipation ltc1605 16-bit, 100ksps, single 5v adc 10v inputs, 55mw, byte or parallel i/o sampling adcs dacs part number description comments ltc1595 16-bit serial multiplying i out dac in so-8 1lsb max inl/dnl, low glitch, dac8043 16-bit upgrade ltc1596 16-bit serial multiplying i out dac 1lsb max inl/dnl, low glitch, ad7543/dac8143 16-bit upgrade ltc1597 16-bit parallel, multiplying dac 1lsb max inl/dnl, low glitch, 4 quadrant resistors ltc1650 16-bit serial v out dac low power, low gritch, 4-quadrant multiplication

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